Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
The common fragment of CTL and LTL
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Formal Methods in System Design
Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Extracting certificates from quantified boolean formulas
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
sKizzo: a suite to evaluate and certify QBFs
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Binary clause reasoning in QBF
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Automatic generation of local repairs for Boolean programs
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Explaining Counterexamples Using Causality
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Evaluating and certifying QBFs: A comparison of state-of-the-art tools
AI Communications
Efficiently solving quantified bit-vector formulas
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Resolution proofs and Skolem functions in QBF evaluation and applications
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Journal of Computer and System Sciences
Explaining counterexamples using causality
Formal Methods in System Design
A uniform approach for generating proofs and strategies for both true and false QBF formulas
IJCAI'11 Proceedings of the Twenty-Second international joint conference on Artificial Intelligence - Volume Volume One
Unified QBF certification and its applications
Formal Methods in System Design
Efficiently solving quantified bit-vector formulas
Formal Methods in System Design
| Hi-index | 0.00 |
In this paper, we study the use of QBF solvers for fault localization and correction of sequential circuits. Given a violated specification, we compute whether the circuit can be repaired by evaluating a sequence of quantified Boolean formulas. If a repair exists, it can be extracted from a certificate for another quantified Boolean formula. Because it only finds components when a repair is possible, this approach is more precise than a satisfiability-based approach that we have developed earlier. We demonstrate this in an experimental evaluation.