Implication of assertion graphs in GSTE

Authors:
Guowu Yang;Jin Yang;William N. N. Hung;Xiaoyu Song
Affiliations:
Portland State University, OR;Intel Corporation, Hillsboro, OR;Intel Corporation, Hillsboro, OR;Portland State University, OR
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 3
Cited 1

Formal verification by symbolic evaluation of partially-ordered trajectories

Formal Methods in System Design - Special issue on symbolic model checking
Introduction to generalized symbolic trajectory evaluation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Maximal models of assertion graph in GSTE

TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation

Quantified Score

Hi-index	0.00

Visualization

Abstract

We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal verification of digital systems. Assertion graphs are used for property and model specifications. We present a novel implication technique for assertion graphs. It relies on direct Boolean reasoning on each edge (and vertex) of an assertion graph, thus avoiding the reachability computation in GSTE. We have successfully applied. both model-based and language-based implications on real industrial circuits. Experimental results demonstrate the promising performance of our approach.