An optimal test compression procedure for combinational circuits

  • Authors:
  • D. S. Hochbaum

  • Affiliations:
  • Dept. of Ind. Eng. & Oper. Res., California Univ., Berkeley, CA

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Year:
  • 2006

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Abstract

The problem of optimal test compression is to derive, from a given set of test vectors, a smallest possible subset of test vectors that still test for the same collection of faults. This achieves optimal compression and largest reduction possible in test time relative to the original set of test vectors. We present a new approach based on the modeling of the problem as the Set Cover problem. Additionally, the approach implies an ordering of the faults according to the difficulty of covering them with the given set of test vectors. As such it can be used to facilitate the finding of a solution to the ultimate smallest test-set-the compression of the set of all possible test vectors. Our approach highlights the potential usefulness of integer programming techniques in testing and design