Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 41st annual Design Automation Conference
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An introductory textbook on cyber-physical systems
WESE '10 Proceedings of the 2010 Workshop on Embedded Systems Education
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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