EST: The new frontier in automatic test-pattern generation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
An Analysis of ATPG and SAT algorithms for Formal Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Forward image computation with backtracing ATPG and incremental state-set construction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
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Computing image/preimage is a fundamental step in formal verification of hardware systems. Conventional OBDD-based methods for formal verification suffer from spatial explosion, since OBDDs can grow exponentially in large designs. On the other hand, SAT/ATPG based methods are less demanding on memory. But the run-time can be huge for these methods, since they must explore an exponential search space. In order to reduce this temporal explosion of SAT/ATPG based methods, efficient learning techniques are needed. In this paper, we present a new ZBDD based method to compactly store and efficiently search previously explored search-states for 'ATPG-based preimage computation'. We learn front these search-states and avoid searching their subsets or supersets. Both,solution and conflict subspaces are pruned based on simple set operations using ZBDDs. We integrate our techniques into an ATPG engine and demonstrate their efficiency on ISCAS '89 benchmark circuits. Experimental results show that significant search-space pruning for preimage computation is achieved, compared to previous methods.