EST: The new frontier in automatic test-pattern generation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation
CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Forward image computation with backtracing ATPG and incremental state-set construction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Fast illegal state identification for improving SAT-based induction
Proceedings of the 43rd annual Design Automation Conference
Existential quantification as incremental SAT
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Symmetry reduction in SAT-based model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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Preimage computation is a key step in formal verification. Pure OBDD-based symbolic method is vulnerable to the space-explosion problem. On the other hand, conventional ATPG/SAT-based method can handle large designs but can suffer from time explosion. Unlike methods that combine ATPG/SAT and OBDD, we present a novel success-driven learning algorithm which significantly accelerates a ATPG engine for enumerating all solutions (preimages). The algorithm effectively prunes redundant search space due to overlapped solutions and constructs a free BDD on the fly so that it becomes the representation of the preimage set at the end. Experimental results have demonstrated the effectiveness of the approach, in which we are able to compute preimages for large sequential circuits, where OBDD-based method fail.