Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Approximate reachability don't cares for CTL model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Formal verification based on assume and guarantee approach — a case study (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Model Checking of Safety Properties
Formal Methods in System Design
Multiple State and Single State Tableaux for Combining Local and Global Model Checking
Correct System Design, Recent Insight and Advances, (to Hans Langmaack on the occasion of his retirement from his professorship at the University of Kiel)
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Model Checking of Safety Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
From Pre-Historic to Post-Modern Symbolic Model Checking
Formal Methods in System Design
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Forward symbolic model checking for real time systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
IEEE Transactions on Computers
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
Interleaved invariant checking with dynamic abstraction
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
On the construction of fine automata for safety properties
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
BDD-Based hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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Forward model checking is an efficient symbolic model checking method for verifying realistic properties of sequential circuits and protocols. In this paper, we present the techniques that modify the order of state traversal on forward model checking, and that dramatically improve average CPU time for finding design errors. A failing property has to be checked again and again to analyze the bug until it is corrected. The techniques, therefore, can have significant impacts on actual verification tasks. We use a modified regular/omega-regular expression to represent a set of illegal state transition sequences of an FSM. It makes the problem clear and gives us a sense of depth-first traversal, not on the state space, but on the property.