Communicating sequential processes
Communicating sequential processes
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automata-Theoretic techniques for modal logics of programs
Journal of Computer and System Sciences
A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
Handbook of theoretical computer science (vol. B)
Handbook of theoretical computer science (vol. B)
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The concurrency workbench: a semantics-based tool for the verification of concurrent systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
A classical mind
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
IEEE Spectrum
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Communication and Concurrency
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
IEEE Transactions on Computers
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This chapter overviewes Binary Decision Diagrams (BDDs) and their application in Formal Hardware Verification. BDDs are first described as a representation formalism for Boolean functions. BDDs are directed acyclic graphs, deriving their efficiency from canonicity, and from their ability to be exponentially more compact, in terms of node count, than alternative Boolean representations. The chapter introduces the main BDD operators, in terms of recursive graph manipulation functions. Some of the most succesful Formal Verification techniques, based on BDD engines, are then reported. The description is limited to Reduced Ordered BDDs (ROBDDs), which, albeight being just one among several decomposition types, are the most widely used and the most general one.