Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Programming from specifications
Programming from specifications
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
The Impact of Branching Heuristics in Propositional Satisfiability Algorithms
EPIA '99 Proceedings of the 9th Portuguese Conference on Artificial Intelligence: Progress in Artificial Intelligence
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
ASE '00 Proceedings of the 15th IEEE international conference on Automated software engineering
Software Abstractions: Logic, Language, and Analysis
Software Abstractions: Logic, Language, and Analysis
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
Bounded model checking of software using SMT solvers instead of SAT solvers
International Journal on Software Tools for Technology Transfer (STTT)
Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Deciding Effectively Propositional Logic Using DPLL and Substitution Sets
Journal of Automated Reasoning
JPF-SE: a symbolic execution extension to Java PathFinder
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Synthesizing biological theories
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
LLBMC: bounded model checking of C and C++ programs using a compiler IR
VSTTE'12 Proceedings of the 4th international conference on Verified Software: theories, tools, experiments
Analyzing temporal properties of abstract models
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
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A main idea underlying bounded model checking is to limit the length of the potential counter-examples, and then prove properties for the bounded version of the problem. In software model checking, that means that only program traces up to a given length are considered. Additionally, the program's input space must be made finite by defining bounds for all input parameters. To ensure the finiteness of the program traces, these techniques typically require that all loops are explicitly unrolled some constant number of times. Here, we show how to avoid explicit loop unrolling by using the SMT Theory of Lists to model feasible, potentially unbounded program traces. We argue that this approach is easier to use, and, more importantly, increases the confidence in verification results over the typical bounded approach. To demonstrate the feasibility of this idea, we implemented a fully automated prototype software model checker and verified several example algorithms. We also applied our technique to a non software model-checking problem from biology - we used it to analyze and synthesize correct executions from scenario-based requirements in the form of Live Sequence Charts.