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The temporal logic of reactive and concurrent systems
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Journal of the ACM (JACM)
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CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
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CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
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SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
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This paper deals with systems verification techniques, using Bounded Model Checking (BMC). We present a new approach that combines BMC with symmetry reduction techniques. Our goal is to reduce the number of transition sequences, which can be handled by a SAT solver, used in the resolution of verification problems. In this paper, we generate a reduced model by exploiting the symmetry of the original model,which contains only transition sequences that represent the equivalence classes of the symmetric transition sequences. We consider the construction of a new Boolean formula that manipulates only representative transition sequences. In our technique, we present a method that combines the symmetry reduction technique with BMC for the reduction of the space and time of Model Checking.