Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Art of Verification with VERA
Design Verification with e
Generating concurrent test-programs with collisions for multi-processor verification
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
An effective and flexible approach to functional verification of processor families
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
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Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments.