A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
Journal of Electronic Testing: Theory and Applications
Low-Cost Software-Based Self-Testing of RISC Processor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using introspective software-based testing for post-silicon debug and repair
Proceedings of the 47th Design Automation Conference
A new SBST algorithm for testing the register file of VLIW processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Instruction-based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper we apply our efficient methodology for processor core self-testing based on the knowledge of its instruction set architecture and register transfer level description on a common accumulator-based processor core benchmark. We also demonstrate that our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while the same fault coverage is achieved with an order of magnitude smaller test application time compared with a recently published structural methodology for processor core self-testing.