Program Slicing for Hierarchical Test Generation

Authors:
Vivekananda M. Vedula;Jacob A. Abraham;Jayanta Bhadra
Affiliations:
-;-;-
Venue:
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Year:
2002

Citing 0
Cited 4

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Journal of Electronic Testing: Theory and Applications
Automatic circuit extractor for HDL description using program slicing

Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
Reducing verification overhead with RTL slicing

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Automatic constraint based test generation for behavioral HDL models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Sequential Automatic Test Pattern Generation (ATPG) is extremely computation intensive and produces good results only on relatively small designs. This paper develops an elegant theoretical basis,based on program slicing, for hierarchical ATPG which targets one module at a time and abstracts the rest of the design. The technique for obtaining a Constraint slice for each embedded Module Under Test (MUT) within a design is described in detail. The technique has been incorporated in an automated tool for designs described in Verilog, and results on large benchmark circuits show the significant benefits of the approach.