Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
The semantic approach to program slicing
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using Program Slicing in Software Maintenance
IEEE Transactions on Software Engineering
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Extracting Reusable Functions by Flow Graph-Based Program Slicing
IEEE Transactions on Software Engineering
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
A Graphical Parallel Composition Operator for Process Algebras
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Slicing Concurrent Programs - A Graph-Theoretical Approach
AADEBUG '93 Proceedings of the First International Workshop on Automated and Algorithmic Debugging
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
Proceedings of the conference on Design, automation and test in Europe
IWPC '01 Proceedings of the 9th International Workshop on Program Comprehension
Program Slicing for Hierarchical Test Generation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Hierarchical test generation under architectural level functional constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic insertion of low power annotations in RTL for pipelined microprocessors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of Electronic Testing: Theory and Applications
Efficient Model Checking of Hardware Using Conditioned Slicing
Electronic Notes in Theoretical Computer Science (ENTCS)
Scaling RTL property checking using feasible path analysisand decomposition
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the design, have shown promising results in reducing the test generation complexity. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical test generation. The technique to systematically obtain a “constraint slice” for each embedded module under test within a design, is described in detail. The technique has been incorporated in an automated tool for Verilog designs, and results on large benchmark circuits show the significant benefits of the approach.