A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Journal of Electronic Testing: Theory and Applications
Program Slicing of Hardware Description Languages
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
DART: directed automated random testing
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
CUTE: a concolic unit testing engine for C
Proceedings of the 10th European software engineering conference held jointly with 13th ACM SIGSOFT international symposium on Foundations of software engineering
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Tunneling and slicing: towards scalable BMC
Proceedings of the 45th annual Design Automation Conference
Bounded model checking of software using SMT solvers instead of SAT solvers
International Journal on Software Tools for Technology Transfer (STTT)
High level static analysis of system descriptions for taming verification complexity
High level static analysis of system descriptions for taming verification complexity
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Property checking at the Register Transfer Level (RTL) is a critical problem for verifying complex digital design. In this paper, we present a scalable solution for property checking at RTL. We check the properties of the form G(A=X=tB), which means that once A is valid, B should be valid t cycles later. We introduce a decomposition strategy to scale high level bounded property checking. This decomposition strategy partitions the monolithic SMT based BMC problem into multiple smaller, independent subproblems. Every path in the RTL program is analyzed for feasibility/relevance using (a) a hybrid of concrete and symbolic execution and (b) property based pruning using the antecedent condition A. The partitions of the RTL source code that correspond to the feasible paths are then checked with respect to the property of interest using an SMT solver. We manage to prune a large percentage of the RTL design paths using feasibility check, such that the decomposed subproblems are small and easily verifiable.