Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
BDD variable ordering for interacting finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hybrid verification using saturated simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Nuts and bolts of core and SoC verification
Proceedings of the 38th annual Design Automation Conference
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Journal of Network and Computer Applications
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The conventional methods cannot easily handle the verification task of increasingly complex hardware designs. This research proposes a novel collaborative scheme for verifying functional properties of a design. The classified properties are designed for three verification engines, i.e. module simulation, BDD-based (Binary Decision Diagram) model checking and CDFG (Control Data Flow Graph) static analysis. The cooperative scheme is performed on a refined model from CDFG structure and three methods are employed to complete the properties verification interactively and collectively. For speeding up the verification process, optimization techniques are introduced, such as variables reordering, properties pre-grouping, and model refining. The benchmarks ITC'99 (International Test Conference) are used to demonstrate the validity and practicality of the collaborative scheme.