Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Concurrent Fault Detection in Random Combinational Logic
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
A Low-Cost Concurrent BIST Scheme for Increased Dependability
IEEE Transactions on Dependable and Secure Computing
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set
IEEE Transactions on Computers
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
ETS '09 Proceedings of the 2009 European Test Symposium
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
Efficient BIST TPG design and test set compaction via input reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A concurrent testing technique for digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Input vector monitoring on line concurrent BIST based on multilevel decoding logic
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.