Dependable design technique for system-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Journal of Electronic Testing: Theory and Applications
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We discuss a non-intrusive methodology for concurrentfault detection in random combinational logic. The proposedmethod is similar to duplication, wherein a replica of thecircuit acts as a predictor that immediately detects potentialfaults by comparison to the original circuit. However,instead of duplicating the circuit, the proposed method selectsa small number of prediction logic functions which onlypartially replicate it. Selection is guided by the objective ofminimizing the incurred hardware overhead at the cost of introducingfault detection latency. To achieve this, the proposedmethod replicates only a reduced width output functionfor every input combination, yet without compromisingthe ability to detect all faults. In contrast to concurrent errordetection schemes which presume the ability to resynthesizethe circuit, the proposed method does not interfere with theimplementation of the original design. As compared to previousapproaches, the proposed method achieves significanthardware overhead reduction, while detecting all faults withvery low average fault detection latency.