Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
A new approach to scan chain reordering using physical design information
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scan insertion criteria for low design impact
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
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For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation during the physical design stage. In this paper, a scan chain ordering technique for test power reduction under user-specified routability constraints is presented. The proposed technique allows the user to explicitly set the routing constraints and the achievable power reduction is rather insensitive to the routing constraints. The proposed method is applied to six industrial designs. The achievable power reduction is in the range of 37--48% without violating any user-specified routing constraint.