CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Survey of Test Vector Compression Techniques
IEEE Design & Test
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Scan cell positioning for boosting the compression of fan-out networks
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Low-power test in compression-based reconfigurable scan architectures
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a technique based on the reconfiguration of scan chains to reduce test time and test data volume for Illinois Scan Architecture (ILS) based designs. This technique is presented with details of hardware implementation as well as the test generation and test application procedures. The reduction in test time and test data volume achieved using this technique is quite signi .cant in most circuits.