High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Improved Handling of False and Multicycle Paths in ATPG
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
At-Speed Testing with Timing Exceptions and Constraints-Case Studies
ATS '06 Proceedings of the 15th Asian Test Symposium
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in [1]. This paper presents a unified and complete algorithm for computing test responses in the presence of timing exceptions with both setup and hold violations, and Boolean timing constraints. The new algorithm analyzes all possible effects of glitches in the circuit. It resolves pessimism in the case of multiple interacting timing exception paths. The new method significantly reduces the number of unknowns in the test responses, resulting in improved test coverage and test compression. The new method can be applied to 1) any fault model, 2) any test pattern, 3) any simulation environment, and/or 4) any test generator.