Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs

Authors:
B. R. Benware;R. Madge;C. Lu;R. Daasch
Affiliations:
-;-;-;-
Venue:
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Year:
2003

Citing 0
Cited 6

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers

IEEE Design & Test
Test generation in the presence of timing exceptions and constraints

Proceedings of the 44th annual Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Statistical defect-detection analysis of test sets using readily-available tester data

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In sub-micron processes, resistive path defectsare increasingly contributing to the yield loss and thecustomer fail pareto. Data has been collected on a seriesof ASIC products and compares the effectiveness of fullvector set transition delay fault tests with reduced vectorsets, minVDD, customer functional tests and customerssystem fails. Results show that fault models do not predictthe defect coverage well and cost effective screening offrequency outliers and minVDD outliers is possible and iscritical in improving customer quality.