IEEE Design & Test
Addressing Early Design-For-Test Synthesis in a Production Environment
Proceedings of the IEEE International Test Conference
Testable Programmable Digital Clock Pulse Control Elements
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Mutating Metric for Benchmarking Test
IEEE Design & Test
IEEE Design & Test
VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform
IEEE Transactions on Computers
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Register-transfer level functional scan for hierarchical designs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 4.10 |
The customer expects defect-free chips, even at consumer prices-making thorough manufacturing test mandatory. With increasing chip density, the addition of say 10,000 gates is no longer of great impact (these would occupy only 0.1 mm2 on adie); satisfying timing requirements and not exceeding package or system power requirements are the principal implementation objectives. The new availability of silicon real estate has transformed the design-for- testability environment. Implementing contemporary application-specific integrated circuit (ASIC) designs based on standard-cell and gate array technologies now requires design flows that incorporate DFT. Robust design for testability in very deep-submicron (VDSM) technologies is essential to volume manufacturing. The most common structural test method is scan-based logic test, which is now the backbone of manufacturing test. Using this method, commercial ATPG tools rely on test-mode reconfiguration of the circuit to a pseudo-combinational one, ensuring its access, controllability, and observability. Each state bit is trans-formed into a stage (either a flip-flop or master-slave latch pair) of a shift register or scan chain accessible from chip pins. The author points out ways to avoid pitfalls in implementing effect scan-based test. These include modifying register-transfer- level circuit representations for testability, using single clock edge design, and providing clock control.