Logic testing and design for testability
Logic testing and design for testability
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Progress in Design for Test: A Personal View
IEEE Design & Test
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
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The authors describe scan path, NEC's implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design and compare four implementations, including two scan-path techniques.