Logic testing and design for testability
Logic testing and design for testability
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Structured Logic Testing
IEEE Design & Test
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing Errors: Data and Calculations in an IC Manufacturing Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
IEEE Design & Test
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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The author discusses the history and benefits of design for test. He describes common arguments against it and gives convincing rebuttals to each. In addition, he provides a glimpse into the future of DFT. The problem is that we do not have a measurable parameter that expresses the incremental gain in product quality arising from the addition of some specific DFT technique, compared to its cost of implementation. The author refers to this parameter as the quality improvement factor (Quif), and defines it as the benefit versus the cost of the DFT technique.