Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Progress in Design for Test: A Personal View
IEEE Design & Test
Synthesizing Circuits with Implicit Testability Constraints
IEEE Design & Test
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An object-oriented approach to the concurrent engineering of electronics assemblies
Computers in Industry
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Everyone knows what test synthesis is. However, few people agree on any given definition. This may result from the fact that both "test" and "synthesis" are vague terms in and of themselves, so combining them results only in additional vagueness. Even so, a wide variety of activities may be included under the test synthesis umbrella, ranging from synthesis of inherently testable circuits to the inclusion of built-in self-test (BIST) circuitry as part of behavioral synthesis to constraining logic synthesis to conform to the rules of standard DFT techniques such as scan. Because much of this work is currently university research, the definition of test synthesis narrows considerably when one is considering tools which may be purchased from EDA (Electronic Design Automation) vendors.Test synthesis is becoming an increasingly important part of circuit design. Time to market and other cost constraints mandate that circuits be designed in ever-decreasing time, often by ever-smaller design teams. Design reuse and logic synthesis are necessary parts of such a methodology. Leaving design-for-testability (DFT) circuitry to be added manually, after logic synthesis, creates an unaffordable design bottleneck. Ignoring DFT altogether can jeopardize product quality and/or introduce schedule delays. When the design process is synthesis-based, design for testability can only be achieved by incorporating test and synthesis into an overall automated (where possible) methodology. There are a number of ways of performing test synthesis.