Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
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VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Journal of Electronic Testing: Theory and Applications
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel x-ploiting strategy for improving performance of test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using efficient bitmask and dictionary selection methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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In this paper we present a new test data compression technique and an associated decompression scheme for testing VLSI chips. Our method is based on our novel use of the much utilized in software LZW, particularly LZ77 algorithm. We adapt LZ77 to accommodate bit strings rather than character sets. Moreover, we exploit the large presence of Don't Cares in the uncompressed test sets that we generated using commercial ATPG tools. Our decompression scheme makes effective use of the on chip boundary scan during decompression and then feeding the internal multiple scan chains for testing. The hardware overhead cost for this scheme is minimal. Experimental results are provided.