Parameterized design and evaluation of bandwidth compressor for floating-point data streams in FPGA-Based custom computing

Authors:
Tomohiro Ueno;Yoshiaki Kono;Kentaro Sano;Satoru Yamamoto
Affiliations:
Graduate School of Information Sciences, Tohoku University, Aoba-ku, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Aoba-ku, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Aoba-ku, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Aoba-ku, Sendai, Japan
Venue:
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Year:
2013

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Abstract

We are applying bandwidth compression to enhance performance of FPGA-based custom computing. This paper presents and evaluates hardware design of a bandwidth compressor and decompressor for a floating-point data stream of various bit width. We show their structures parameterized for a bit width of an input word. Through FPGA-based prototype implementation, we evaluate the resource utilization, frequency, and compression ratio. The expermental results show that the compressor and decompressor for 32-bit and 64-bit floating-point numbers achieve bandwidth reduction at a ratio of 3.1 and 1.8 for 2D data of fluid dynamics computation, while they require only small area and operate at higher than 200MHz.