Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
IEEE Transactions on Computers
Frequent value compression in data caches
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
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ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
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IEEE Micro
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DCC '96 Proceedings of the Conference on Data Compression
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Proceedings of the 30th annual international symposium on Computer architecture
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Proceedings of the 2003 international symposium on Low power electronics and design
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Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
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Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the 31st annual international symposium on Computer architecture
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Proceedings of the 31st annual international symposium on Computer architecture
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Proceedings of the 32nd annual international symposium on Computer Architecture
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Proceedings of the 32nd annual international symposium on Computer Architecture
IBM memory expansion technology (MXT)
IBM Journal of Research and Development
Decoupled zero-compressed memory
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
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We propose a checkpoint store compression method for coarse-grain giga-scale checkpoint/restore. This mechanism can be useful for debugging, post-mortem analysis and error recovery. Our compression method exploits value locality in the memory data and address streams. Our compressors require few resources, can be easily pipelined and can process a full cache block per processor cycle. We study two applications of our compressors for post-mortem analysis: (1) Using them alone, and (2) using them in-series with a dictionary-based compressor. When used alone they offer competitive compression rates in most cases. When combined with dictionary compressors, they significantly reducing onchip buffer requirements.