The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Procedure based program compression
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Frequent value locality and value-centric data cache design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Design and Evaluation of a Selective Compressed Memory System
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Automatic Generation of Microarchitecture Simulators
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
Exploiting program redundancy to improve performance, cost and power consumption in embedded systems
Exploiting program redundancy to improve performance, cost and power consumption in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Data Compression Transformations for Dynamically Allocated Data Structures
CC '02 Proceedings of the 11th International Conference on Compiler Construction
The performance advantage of applying compression to the memory system
Proceedings of the 2002 workshop on Memory system performance
Generating physical addresses directly for saving instruction TLB energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Energy efficient frequent value data cache design
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Power protocol: reducing power dissipation on off-chip data buses
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 2003 international symposium on Low power electronics and design
Exploiting Value Locality in Physical Register Files
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Improving 64-Bit Java IPF Performance by Compressing Heap References
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
Optimizing instruction TLB energy using software and hardware techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory State Compressors for Giga-Scale Checkpoint/Restore
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Profiling over Adaptive Ranges
Proceedings of the International Symposium on Code Generation and Optimization
Optimizing bus energy consumption of on-chip multiprocessors using frequent values
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Parallel, distributed and network-based processing
Proceedings of the 21st annual international conference on Supercomputing
Increasing cache capacity through word filtering
Proceedings of the 21st annual international conference on Supercomputing
Leakage energy reduction in cache memory by data compression
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Formulating and implementing profiling over adaptive ranges
ACM Transactions on Architecture and Code Optimization (TACO)
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Frequent value compression in packet-based NoC architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 23rd international conference on Supercomputing
Using data compression for increasing memory system utilization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient lookahead routing and header compression for multicasting in networks-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A frequent-value based PRAM memory architecture
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Dynamic dictionary-based data compression for level-1 caches
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Dynamic co-allocation of level one caches
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
A space-efficient on-chip compressed cache organization for high performance computing
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures
Proceedings of the great lakes symposium on VLSI
Base-delta-immediate compression: practical data compression for on-chip caches
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Linearly compressed pages: a main memory compression framework with low complexity and low latency
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Linearly compressed pages: a low-complexity, low-latency main memory compression framework
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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