Frequent value compression in data caches
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Effective algorithms for cache-level compression
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Cache-Memory Interfaces in Compressed Memory Systems
IEEE Transactions on Computers
Improving System Performance with Compressed Memory
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
The performance advantage of applying compression to the memory system
Proceedings of the 2002 workshop on Memory system performance
Energy efficient frequent value data cache design
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Improving 64-Bit Java IPF Performance by Compressing Heap References
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
A Content Aware Integer Register File Organization
Proceedings of the 31st annual international symposium on Computer architecture
Optimizing Address Code Generation for Array-Intensive DSP Applications
Proceedings of the international symposium on Code generation and optimization
Selective main memory compression by identifying program phase changes
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Compiler-Guided data compression for reducing memory consumption of embedded applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 21st annual international conference on Supercomputing
Increasing cache capacity through word filtering
Proceedings of the 21st annual international conference on Supercomputing
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Using data compression for increasing memory system utilization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms and data structures for compressed-memory machines
IBM Journal of Research and Development
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C-pack: a high-performance microprocessor cache compression algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory energy minimization by data compression: algorithms, architectures and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Compressed swapping for NAND flash memory based embedded systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compressed form. However, decompression time causes a critical effect on the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed cache architecture. This paper suggests several techniques to reduce the decompression overhead and to manage the compressed blocks efficiently, which include selective compression, fixed space allocation for the compressed blocks, parallel decompression, the use of a decompression buffer, and so on. Moreover, a simple compressed cache architecture based on the above techniques and its management method are proposed. The results from trace-driven simulation show that this approach can provide around 35% decrease in the on-chip cache miss ratio as well as a 53% decrease in the data traffic over the conventional memory systems. Also, a large amount of the decompression overhead can be reduced, and thus the average memory access time can also be reduced by maximum 20% against the conventional memory systems.