ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Frequent value compression in data caches
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Frequent value locality and value-centric data cache design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Parallel compression with cooperative dictionary construction
DCC '96 Proceedings of the Conference on Data Compression
Analysis of simulation-adapted SPEC 2000 benchmarks
ACM SIGARCH Computer Architecture News
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
Proceedings of the conference on Design, automation and test in Europe
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
Operating Systems Concepts with Java
Operating Systems Concepts with Java
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In order to alleviate the ever-increasing processor-memory performance gap of high-end parallel computers, on-chip compressed caches have been developed that can reduce the cache miss count and off-chip memory traffic by storing and transferring cache lines in a compressed form. However, we observed that their performance gain is often limited due to their use of the coarse-grained compressed cache line management which incurs internally fragmented space. In this paper, we present the fine-grained compressed cache line management which addresses the fragmentation problem, while avoiding an increase in the metadata size such as tag field and VM page table. Based on the SimpleScalar simulator with the SPEC benchmark suite, we show that over an existing compressed cache system the proposed cache organization can reduce the memory traffic by 15%, as it delivers compressed cache lines in a fine-grained way, and the cache miss count by 23%, as it stores up to three compressed cache lines in a physical cache line.