Non redundant data cache

Authors:
Carlos Molina;Carles Aliagas;Montse García;Antonio Gonzàlez;Jordi Tubella
Affiliations:
Universitat Rovira i Virgili, Tarragona, SPAIN;Universitat Rovira i Virgili, Tarragona, SPAIN;Universitat Rovira i Virgili, Tarragona, SPAIN;Universitat Politècnica de Catalunya, Barcelona, SPAIN and Intel Labs-Univ. Politècnica de Catalunya, Barcelona, SPAIN;Universitat Politècnica de Catalunya, Barcelona, SPAIN
Venue:
Proceedings of the 2003 international symposium on Low power electronics and design
Year:
2003

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Abstract

Current microprocessors spend a huge percentage of the die area to implement the memory hierarchy. Moreover, cache memory is responsible for a significant percentage of the total energy consumption. This paper presents a novel data cache design to reduce its die area, power dissipation and latency. The new scheme, called Non Redundant Cache (NRC), exploits the immense amount of value replication observed in traditional data caches. The NRC cache significantly reduces the storage requirements by avoiding the replication of values. Results show that the NRC cache reduces the die area in a 32%, the power dissipation by 14% and the latency by 25%, while maintaining the miss ratio of a conventional cache.