Dynamic co-allocation of level one caches

Authors:
Lingling Jin;Wei Wu;Jun Yang;Chuanjun Zhang;Youtao Zhang
Affiliations:
University of California at Riverside, Riverside, CA;University of California at Riverside, Riverside, CA;University of California at Riverside, Riverside, CA;University of Missouri at Kansas City, Kansas City, MO;University of Texas at Dallas, Richardson, TX
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

The effectiveness of level one (L1) caches is of great importance to the processor performance. We have observed that programs exhibit varying demands in the L1 instruction cache (I-cache) and data cache (D-cache) during execution, and such demands are notably different across programs. We propose to co-allocate the cache ways between the I- and D-cache in responses to the program’s need on-the-fly. Resources are re-allocated based on the potential performance benefit. Using this scheme, a 32KB co-allocation L1 can gain 10% performance improvement on average, which is comparable to a 64KB traditional L1.