UNIX internals: the new frontiers
UNIX internals: the new frontiers
Predicting indirect branches via data compression
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
On management of free space in compressed memory systems
SIGMETRICS '99 Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Parallel compression with cooperative dictionary construction
DCC '96 Proceedings of the Conference on Data Compression
Performance of Hardware Compressed Main Memory
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
The case for compressed caching in virtual memory systems
ATEC '99 Proceedings of the annual conference on USENIX Annual Technical Conference
Algorithms and data structures for compressed-memory machines
IBM Journal of Research and Development
Cache-Memory Interfaces in Compressed Memory Systems
IEEE Transactions on Computers
Hardware Compressed Main Memory: Operating System Support and Performance Evaluation
IEEE Transactions on Computers
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Improving disk bandwidth-bound applications through main memory compression
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithms and data structures for compressed-memory machines
IBM Journal of Research and Development
Memory expansion technology (MXT): competitive impact
IBM Journal of Research and Development
Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Base-delta-immediate compression: practical data compression for on-chip caches
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Linearly compressed pages: a main memory compression framework with low complexity and low latency
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Linearly compressed pages: a low-complexity, low-latency main memory compression framework
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 0.01 |
A novel memory subsystem called Memory Expansion Technology (MXT) has been built for fast hardware compression of main-memory content. This allows a memory expansion to present a "real" memory larger than the physically available memory. This paper provides an overview of the memory-compression architecture, its OS support under Linux and Windows®, and an analysis of the performance impact of memory compression. Results show that the hardware compression of main memory has a negligible penalty compared to an uncompressed main memory, and for memory-starved applications it increases performance significantly. We also show that the memory content of an application can usually be compressed by a factor of 2.