Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs

  • Authors:
  • K. Inoue;K. Kai;K. Murakami

  • Affiliations:
  • -;-;-

  • Venue:
  • HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
  • Year:
  • 1999

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Abstract