Performance of a shared memory system for vector multiprocessors
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Alleviation of tree saturation in multistage interconnection networks
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
The cedar system and an initial performance study
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
Compiler-Directed Cache Assist Adaptivity
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
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Cedar scalability is studied via simulation and measurement. The simulation methodology is verified by comparing simulated performance with that of the real machine. The performance scalability of the interconnection networks and memory modules which compose Cedar's shared memory system is then examined in detail. The system is shown to be basically scalable in performance, but not perfectly so. A "brute force" approach to increasing scalability, doubling the clock speed of the memory subsystem, is shown to be only moderately effective at improving scalability. Finally, by limiting traffic in the network, the scalablity of the system is increased signficantly at very little cost.