Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
System design methodologies for a wireless security processing platform
Proceedings of the 39th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Frame-based dynamic voltage and frequency scaling for a MPEG decoder
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
The M"CORE(TM) M340 Unified Cache Architecture
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interactive presentation: Soft-core processor customization using the design of experiments paradigm
Proceedings of the conference on Design, automation and test in Europe
Dynamic tuning of configurable architectures: the AWW online algorithm
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
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General-purpose System-on-Chip platforms consistingof configurable components are emerging as an attractivealternative to traditional, customized solutions (e.g., ASICs,custom SoCs), owing to their flexibility, time-to-market advantage,and low engineering costs. However, the adoptionof such platforms in many high-volume markets (e.g, wirelesshandhelds) is limited by concerns about their performance andenergy-efficiency. This paper addresses the problemof enablingthe use of configurable platforms in domains where custom approacheshave traditionally been used. We introduce DynamicPlatform Management, a methodology for customizing a configurablegeneral-purpose platform at run-time, to help bridgethe performance and energy efficiency gap with custom approaches.The proposed technique uses a software layer that detectstime-varying processing requirements imposed by a set ofapplications, and dynamically optimizes architectural parametersand platform components. Dynamic platform managementenables superior application performance, more efficient utilizationof platform resources, and improved energy efficiency,as compared to a statically optimized platform, without requiringany modifications to the underlying hardware.We illustrate dynamic platform management by applying itto the design of a dual-access UMTS/WLANsecurity processingsystem, implemented on a general-purpose configurable platform.Experiments demonstrate that, compared to a staticallyoptimized design (on the same platform), the proposed techniquesenable upto 33% improvements in security processingthroughput, while achieving 59% savings in energy consumption(on average).