Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms

Authors:
Alexander Maxiaguine;Samarjit Chakraborty;Simon Kunzli;Lothar Thiele
Affiliations:
Swiss Federal Institute of Technology;National University of Singapore;Swiss Federal Institute of Technology;Swiss Federal Institute of Technology
Venue:
IEEE Design & Test
Year:
2004

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Abstract

Editors' note:Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.--Radu Marculescu, Carnegie Mellon University; and Petru Eles, LinköpingUniversity