Stride directed prefetching in scalar processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Sector Cache Design and Performance
Sector Cache Design and Performance
Hitting the Memory Wall: Implications of the Obvious
Hitting the Memory Wall: Implications of the Obvious
Designing real-time H.264 decoders with dataflow architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
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The off-chip memory communication is often a critical part of a video processing system. Traditional cache usually behaves poor since some video algorithms such as H.264 motion compensation tend to access memory in an inefficient way. Based on the analysis of cache line fetch efficiency, we find out that more than 10% fetches are inefficient. In this paper, we propose a Heterogeneous Associative Cache (HA Cache) architecture, in which there is an additional special way with a smaller cache line size, special mapping strategy and replacement policy. This scheme can effectively reduce power, cache space, and bandwidth wasted on useless data. By adding a special way to the traditional 2-way set-associative cache (with 1/8 cache size increase), the HA Cache can save up to 10% memory access. In most cases, it is even better than doubling the traditional cache size.