Adaptive line size cache for irregular references on cell multicore processor

Authors:
Qian Cao;Chongchong Zhao;Junxiu Chen;Yunxing Zhang;Yi Chen
Affiliations:
University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China
Venue:
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Year:
2010

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Abstract

Software cache promises to achieve programmability on Cell processor. However, irregular references couldn't achieve a considerable performance improvement since the cache line is always set to a specific size. In this paper, we propose an adaptive cache line prefetching strategy which continuously adjusts cache line size during application execution. Therefore, the transferred data is decreased significantly. Moreover, a corresponding software cache - adaptive line size cache is designed. It introduces a hybrid Tag Entry Arrays, with each mapping to a different line size. It's a hierarchical design in that the misshandler is not invoked immediately when an address is a miss in the short line Tag Entry Array. Instead, the long line Tag Entry Array is checked first, which significantly increases the hit rate. Evaluations indicate that improvement due to the adaptive cache line strategy translates into 3.29 to 5.73 speedups compared to the traditional software cache approach.