MIPS RISC architecture
Second bibliography on Cache memories
ACM SIGARCH Computer Architecture News
Cache write policies and performance
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
Exploiting spatial locality in data caches using spatial footprints
Proceedings of the 25th annual international symposium on Computer architecture
Adapting cache line size to application behavior
ICS '99 Proceedings of the 13th international conference on Supercomputing
Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through
Journal of the ACM (JACM)
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Proceedings of the 27th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Using a user-level memory thread for correlation prefetching
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Estimating influence of data layout optimizations on SDRAM energy consumption
Proceedings of the 2003 international symposium on Low power electronics and design
Energy aware lossless data compression
Proceedings of the 1st international conference on Mobile systems, applications and services
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A Robust Main-Memory Compression Scheme
Proceedings of the 32nd annual international symposium on Computer Architecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
DRAM energy reduction by prefetching-based memory traffic clustering
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs
Proceedings of the 50th Annual Design Automation Conference
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DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high, exceeding that of the data cache or even that of the processor. This paper presents and evaluates a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small, cachelike structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption, 23%, on average, and reduction in the energy-delay product, 44%, on average. The approach also improves performance: the CPI is reduced by 26%, on average.