Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems

Authors:
L. Nachtergaele;F. Catthoor;F. Balasa;F. Franssen;E. De Greef;H. Samsom;H. De Man
Affiliations:
-;-;-;-;-;-;-
Venue:
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Year:
1995

Citing 0
Cited 17

Power exploration for data dominated video applications

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Fast and extensive system-level memory exploration for ATM applications

ISSS '97 Proceedings of the 10th international symposium on System synthesis
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach

Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
System-Level Data-Flow Transformation Exploration andPower-Area Trade-offs Demonstrated on Video Codecs

Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Trade-Off Analysis of a Low-Power Image Coding Algorithm

Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache

Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
Interactive co-design of high throughput embedded multimedia

Proceedings of the 37th Annual Design Automation Conference
DCT-Domain Embedded Memory Compression for Hybrid Video Coders

Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
A decade of reconfigurable computing: a visionary retrospective

Proceedings of the conference on Design, automation and test in Europe
System level memory optimization for hardware-software co-design

Readings in hardware/software co-design
Tuning of loop cache architectures to programs in embedded system design

Proceedings of the 15th international symposium on System Synthesis
Multi-dimensional Selection Techniques for Minimizing Memory Bandwidth in High-Throughput Embedded Systems

HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Synthesis of customized loop caches for core-based embedded systems

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
System level memory optimization for hardware-software co-design

CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Flow Graph Balancing for Minimizing the Required Memory Bandwidth

ISSS '96 Proceedings of the 9th international symposium on System synthesis
Code Transformations for Low Power Caching in Embedded Multimedia Processors

IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Quantified Score

Hi-index	0.00

Visualization

Abstract

This overview paper discusses sore of the system opportunities and the manufacturing costs of integrating large amounts of logic and memory on a single chip.