The cache performance and optimizations of blocked algorithms
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Data and computation transformations for multiprocessors
PPOPP '95 Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming
Formalized methodology for data reuse exploration in hierarchical memory mappings
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Analysis of power consumption in memory hierarchies
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
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Dependence Analysis for Supercomputing
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Image and Video Compression Standards: Algorithms and Architectures
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A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
A Unified Transformation Technique for Multilevel Blocking
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing - Volume I
System-Level Memory Management for Weakly Parallel Image Processing
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
Automatic data mapping of signal processing applications
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Memory Organization for Improved Data Cache Performance in Embedded Processors
ISSS '96 Proceedings of the 9th international symposium on System synthesis
IEEE Transactions on Circuits and Systems for Video Technology
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Cache conscious data layout organization for embedded multimedia applications
Proceedings of the conference on Design, automation and test in Europe
Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Advanced Data Layout Optimization for Multimedia Applications
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Optimal Code and Data Layout in Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Analysis and Modeling of Energy Reducing Source Code Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Instruction code mapping for performance increase and energy reduction in embedded computer systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-parametric improvements for embedded systems using code-placement and address bus coding
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the conference on Design, automation and test in Europe
Code transformation and instruction set extension
ACM Transactions on Embedded Computing Systems (TECS)
Context-independent codes for off-chip interconnects
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
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In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processing applications. Our methodology is targeted towards embedded multi-media and DSP processors. This methodology takes into account many program parameters like the locality of data, size of data structures, access structures of large array variables, regularity of loop nests and the size and type of cache with the objective of improving the cache performance for lower power. We also take into account the potential overhead due to the different transformations on the instruction count and the number of execution cycles to meet the real time constraints and code size limitations. Experiments on a real life demonstrator illustrate the fact that our methodology is able to achieve significant gain in power requirements while meeting all other system constraints.