Proceedings of the 11th international symposium on System synthesis
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
MPEG-4 Video and Image Coding on Digital Signal Processors
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Proceedings of the 14th international symposium on Systems synthesis
Practical parallel computing
Code Transformations for Low Power Caching in Embedded Multimedia Processors
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Global memory optimisation for embedded systems allowed by code duplication
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
High performance architecture of an application specific processor for the H.264 deblocking filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Systematic preprocessing of data dependent constructs for embedded systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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A program transformation strategy is presented that is able to reduce the buffer size and power consumption for a relatively large class of (pseudo)regular data-dominated signal processing algorithms. Our methodology is targeted toward an implementation on programmable processors, but most of the principles remain valid for a custom processor implementation. As power and area cost are crucial in the context of embedded multimedia applications, this strategy can be very valuable. The feasibility of our approach is demonstrated on a representative high-speed video processing algorithm for which we obtain a substantial reduction of the area and power consumption compared to the classical approaches