System-Level Memory Management for Weakly Parallel Image Processing

System-Level Data-Flow Transformation Exploration andPower-Area Trade-offs Demonstrated on Video Codecs

Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems

Journal of VLSI Signal Processing Systems - Special issue on system level design

System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache

Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation

Analysis of high-level address code transformations for programmable processors

DATE '00 Proceedings of the conference on Design, automation and test in Europe

How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level

DATE '00 Proceedings of the conference on Design, automation and test in Europe

A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints

Journal of VLSI Signal Processing Systems

Data and memory optimization techniques for embedded systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)

System level memory optimization for hardware-software co-design

Readings in hardware/software co-design

Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors

IEEE Design & Test

Interaction Between Data Parallel Compilation and Data Transfer and Storage Cost Minimization for Multimedia Applications

Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing

Interaction between parallel compilation and data transfer and storage cost minimization for multimedia applications

Practical parallel computing

System level memory optimization for hardware-software co-design

CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design

Address Code and Arithmetic Optimizations for Embedded Systems

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Code Transformations for Low Power Caching in Embedded Multimedia Processors

IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium