Background memory area estimation for multidimensional signal processing systems
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Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cache conscious data layout organization for embedded multimedia applications
Proceedings of the conference on Design, automation and test in Europe
Dynamic management of scratch-pad memory space
Proceedings of the 38th annual Design Automation Conference
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
An Efficient Data Partitioning Method for Limited Memory Embedded Systems
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Code Transformations for Low Power Caching in Embedded Multimedia Processors
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Variable partitioning for dual memory bank DSPs
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Local memory exploration and optimization in embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software transactional memory for multicore embedded systems
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
ACM Transactions on Embedded Computing Systems (TECS)
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Efficient layout of code and data sections in varioustypes/levels of memory in an embedded systemsis very critical not only for achieving real-time perormance, but also for reducing its cost and powerconsumption. In this paper we formulate the optimalcode and data section layout problem as an integerlinear programming (ILP problem. The proposedormulation can handle: (i) on-chip and off-chipmemory, (ii) multiple on-chip memory banks, (iii) singleand dual ported on-chip RAMs, (iv) overlay ofdata sections, and (v) swapping of code and data(from/to external memory). Our experiments demonstratethat, or a moderately complex embedded system,the optimal results produced by our formulationtook only a ew minutes on a PC, and it matches, interms of performance and on-chip memory size, with ahand-optimized code/data layout which took 1 man-month.