Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cache conscious data layout organization for embedded multimedia applications
Proceedings of the conference on Design, automation and test in Europe
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Code Transformations for Low Power Caching in Embedded Multimedia Processors
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Frequent value encoding for low power data buses
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Energy reduction in VLSI computation modules: an information-theoretic approach
IEEE Transactions on Information Theory
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces the concept of context-independent coding using frequency-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. In this paper, a single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.1% degradation in performance.