Dataflow-driven memory allocation for multi-dimensional signal processing systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Integration, the VLSI Journal
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Data driven signal processing: an approach for energy efficient computing
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Formalized methodology for data reuse exploration in hierarchical memory mappings
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power storage cycle budget distribution tool support for hierarchical graphs
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Improved force-directed scheduling in high-throughput digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient general-purpose image compression with binary tree predictive coding
IEEE Transactions on Image Processing
Low-power systems on chips (SOCs)
Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power storage cycle budget distribution tool support for hierarchical graphs
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Global interconnect trade-off for technology over memory modules to application level: case study
Proceedings of the 2003 international workshop on System-level interconnect prediction
Low-power design of turbo decoder with exploration of energy-throughput trade-off
Compilers and operating systems for low power
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 1st conference on Computing frontiers
Energy estimation of peripheral devices in embedded systems
Proceedings of the 14th ACM Great Lakes symposium on VLSI
EURASIP Journal on Applied Signal Processing
| Hi-index | 0.00 |
In contrast to current design practice for (programmable) processor mapping, which mainly targets performance, we focus on a systematic trade-off between cycle budget and energy consumed in the background memory organization. The latter is a crucial component in many of todays designs, including multi-media, network protocols and telecom signal processing. We have a systematic way and tool to explore both freedoms and to arrive at Pareto charts, in which for a given application the lowest cost implementation of the memory organization is plotted against the available cycle budget per submodule. This by making optimal usage of a parallelized memory architecture. We indicate, with results on a digital audio broadcasting receiver and an image compression demonstrator, how to effectively use the Pareto plot to gain significantly in overall system energy consumption within the global real-time constraints.