Improving Cache Locality by a Combination of Loop and Data Transformations
IEEE Transactions on Computers - Special issue on cache memory and related problems
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing memory requirements of nested loops for embedded systems
Proceedings of the 38th annual Design Automation Conference
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Storage Management Programmable Process
Storage Management Programmable Process
Global interconnect trade-off for technology over memory modules to application level: case study
Proceedings of the 2003 international workshop on System-level interconnect prediction
Data Reuse Exploration Techniques for Loop-Dominated Applications
Proceedings of the conference on Design, automation and test in Europe
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
| Hi-index | 0.00 |
Data transfer and storage issues "take the centre stage" in information and communication systems because of the increasing complexity and data dominance typically associated to them. In this paper, we summarise a systematic methodology for the power critical storage modules such as local SRAMs. We focus on their memory organisation (access schedule and data assignment) together with an exploration of the effect that the interconnect technology may have on the energy consumed by these local memory organisations in deep sub-micron technologies.